priority-map-fixed.patch
priority-map.patch
[CCACHE-27] Missing LU and LRU is linear complexity - performance Created: 04/Sep/12 Updated: 12/Sep/12 |
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| Status: | Open |
| Project: | core.cache |
| Component/s: | None |
| Affects Version/s: | None |
| Fix Version/s: | None |
| Type: | Defect | Priority: | Major |
| Reporter: | Ghadi Shayban | Assignee: | Fogus |
| Resolution: | Unresolved | Votes: | 0 |
| Labels: | enhancement, performance | ||
| Environment: |
Mac Oracle JDK, Linux OpenJDK |
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| Attachments: |
priority-map-fixed.patch
priority-map.patch
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| Patch: | Code |
| Description |
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Profiling some code with YourKit showed a hotspot in cache statistics on (miss) for LU and LRU caches. Basically two issues: (count (keys {....})) is a count of a seq, not efficient. Replaced with a count of the map. Secondly, (apply f anything) is slow. Profiler showed that the (apply min-key) was really slow. This is mitigated by using a c.d.priority-map instead. On a priority-map, (ffirst {}) or (first (peek {}). Also inverted the logic for threshold comparison. Since there is a (build-leastness-queue) that populates statistics, should caches should favor codepaths for the state of being full all the time? |
| Comments |
| Comment by Ghadi Shayban [ 06/Sep/12 10:49 PM ] |
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I take back the part about (apply) being slow. I think it's more the fact that it's doing a linear scan on keys every single time. (apply) does show up a lot in a profiler, but I haven't figured out why. (apply + (range big)) seems to even be slightly faster than (reduce +) on the same range. |
| Comment by Ghadi Shayban [ 12/Sep/12 9:27 AM ] |
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Patch in proper format |
[CCACHE-22] Change limit parameter name in TTLCache Created: 30/Mar/12 Updated: 15/Jun/12 Resolved: 15/Jun/12 |
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| Status: | Resolved |
| Project: | core.cache |
| Component/s: | None |
| Affects Version/s: | None |
| Fix Version/s: | None |
| Type: | Enhancement | Priority: | Trivial |
| Reporter: | Sebastián Bernardo Galkin | Assignee: | Fogus |
| Resolution: | Completed | Votes: | 0 |
| Labels: | enhancement, patch,, ttl | ||
| Attachments: |
Changed-limit-parameter-name-in-TTLCache.patch
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| Patch: | Code |
| Description |
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"limit" is used in other caches to represent quantity, for TTL it represents time. Using the same name is confusing |
| Comments |
| Comment by Fogus [ 15/Jun/12 1:48 PM ] |
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Changed to :ttl-ms |
[CCACHE-4] Added LIRS factory fn Created: 06/Dec/11 Updated: 08/Dec/11 Resolved: 08/Dec/11 |
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| Status: | Resolved |
| Project: | core.cache |
| Component/s: | None |
| Affects Version/s: | None |
| Fix Version/s: | None |
| Type: | Task | Priority: | Major |
| Reporter: | Fogus | Assignee: | Fogus |
| Resolution: | Completed | Votes: | 0 |
| Labels: | cache, enhancement | ||
| Description |
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LIRS is implemented as a type only ATM. There should also be a corresponding factory fn. |
| Comments |
| Comment by Fogus [ 08/Dec/11 12:11 PM ] |
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Completed in f4d1bf9f1069ba875a7a6a8a65646b35c6fbfd8f |